Data multiplexing device and data multiplexing method, and data transmitter

ABSTRACT

A data multiplexing apparatus or the like is suitable for use with a digital satellite broadcasting system or the like. Inputted video data PESa may be converted by a P/S converter ( 142 ) in the form of parallel data of byte unit to serial data and then may be written in a buffer ( 143 ) and stored therein. Data stored in the buffer may be read out under control of a multiplexing control section ( 135 ). The data thus read out may be converted by a S/P converter ( 144 ) in the form of serial data to parallel data of byte unit and thereby generated as outputted data PDa. When the data storage quantity of buffer increases, under control of a rate-variable control section ( 147 ), a data quantity may be reduced by discarding DCT coefficients of high-orders, for example, with reference to analyzed result of a data analyzing section ( 146 ) and thereby the rate may be varied. Thus, the increase of the data storage quantity of buffer can be suppressed and the increase of the delay time caused when inputted data are multiplexed can be avoided. Therefore, there can be prevented a disadvantage such as a failure of synchronization on the receiving side.

TECHNICAL FIELD

This invention relates to a data multiplexing apparatus and a datamultiplexing method and a data transmitting apparatus for use with adigital satellite broadcasting system, for example.

BACKGROUND ART

Recently, a digital satellite broadcasting system becomes widespreadincreasingly. This system may transmit a bit stream obtained when videoand audio signals are digitally compression-coded according to the MPEGstandard or the like and multiplexed according to the MPEG standard orthe like through a satellite. The receiving side may receive such bitsteam, separate video and audio data from the received bit stream anddecode the resultant bit stream to provide video and audio signals.

As the bit stream, there may be used an MPEG2 (Moving Picture ExpertsGroup 2) transport stream. FIG. 15B shows the MPEG2 transport streamwhich may comprise a series of 188-byte fixed length transport streampackets (hereinafter referred to as “TS packets”) of #1 to #3 programs.Each TS packet may comprise a 4 byte packet header and a 184 byteadaptation field and/or payload as shown in FIG. 15A.

The packet header may comprise a sync byte for detecting the leadingportion of the TS packet, PID (Packet Identification: packetidentification data) indicative of an attribute of individual stream(data string) of the corresponding packet and adaptation field controlinformation indicating whether this packet has the adaptation field andwhether this packet has the payload, or the like. The adaptation fieldmay include added information concerning individual stream and stuffingbytes (invalid data bytes). The payload may comprise video and audioPESs (Packetized Elementary Stream) which are re-divided.

Heretofore, there had been put into practical use the technologiescapable of improving a picture quality and a transmission efficiency byprocessing inputted data at a variable rate. A data multiplexingapparatus is able to multiplex a plurality of variable-rate inputteddata by using a technology such as statistical multiplexing. However,because inputted data is processed at the variable rate, there arisevarious problems such that a delay in the multiplexing is increased bycomplexity of control and that excessive restrictions are imposed uponthe encoder side.

FIG. 16 shows an example of the manner in which a total sum of inputtedrates is fluctuated when inputted data concerning video signals Va, Vb,Vc are multiplexed. During a time period ranging from a time t1 to atime t2, the total sum of inputted rates exceeds an output transmissionrate R1 so that data obtained in that time period cannot be transmittedor can be transmitted after having delayed within a buffer. When dataare allowed to be delayed within the buffer, if the transmission rate isof the fixed transmission rate, then a quantity in which data are storedin the buffer will increase or decrease depending upon a degree in whichthe input rate can be varied. As a result, in some cases, a delay timerequired when inputted data are multiplexed increases considerably tocause a synchronization to be failed on the receiving side, which thenleads to the interruption of an image and sounds. Therefore, thetransmitting side should prevent such accident.

Moreover, when inputted data having priority information aremultiplexed, in general, inputted data with a high priority may bemultiplexed with a priority and other inputted data are stored in thebuffer during that time period. Therefore, in this case, the fluctuationof the quantity in which data are stored in the buffer may become moreremarkable.

It is an object of this invention to provide a data multiplexingapparatus or the like in which the increase of the delay time causedwhen inputted data are multiplexed can be avoided to prevent adisadvantage such as a failure of synchronization on the receiving side.

DISCLOSURE OF THE INVENTION

A data multiplexing apparatus according to this invention comprises aplurality of buffers for respectively storing a plurality of inputteddata, a storage quantity detecting means for detecting data storagequantities of a plurality of buffers, an output data generating meansfor generating a plurality of outputted data by reducing data quantitiesof data stored in a plurality of buffers and a data multiplexing meansfor outputting multiplexed data by multiplexing a plurality of outputteddata.

Also, a data multiplexing method according to this invention comprisesthe steps of storing a plurality of inputted data in a plurality ofbuffers, detecting respectively storage quantities of a plurality ofbuffers, generating a plurality of outputted data by reducing dataquantities of data stored in a plurality of buffers and outputtingmultiplexed data by multiplexing a plurality of outputted data.

Also, a data transmitting apparatus according to this inventioncomprises a data multiplexing section for outputting multiplexed data bymultiplexing a plurality of inputted data and a data transmittingsection for transmitting this multiplexed data, wherein the datamultiplexing section comprises a plurality of buffers for respectivelystoring a plurality of inputted data, a storage quantity detecting meansfor detecting the data storage quantities of a plurality of buffers, anoutput data generating means for generating a plurality of outputteddata by reducing data quantities of data stored in a plurality ofbuffers and a data multiplexing means for outputting multiplexed data bymultiplexing a plurality of outputted data.

In this invention, a plurality of inputted data are supplied to andwritten in a plurality of buffers each comprising an FIFO or the like.There can be obtained a plurality of outputted data by reducing dataquantities of data stored in a plurality of buffers in response to therespective data storage quantities. In this case, the data reductionquantity may increase as the data storage quantity increases.

Incidentally, the data quantities may be reduced with reference to thedata storage quantities, the transmission rate and the priority ofinputted data. For example, when the transmission rate is large, thereduction quantity may be decreased. When the transmission rate issmall, the reduction quantity may be increased. Also, for example, whenthe priority is high, the reduction quantity may be decreased. When thepriority is low, the reduction quantity may be increased. When theinputted data is data which is compressed by using a discrete cosinetransformation, it becomes possible to reduce the data quantity bydiscarding high-order coefficients of the discrete cosinetransformation.

There can be obtained multiplexed data by multiplexing a plurality ofoutputted data which are obtained by reducing the data quantities asdescribed above. Then, this multiplexed data is transmitted to thereceiving side. As described above, a plurality of outputted data areobtained by reducing the data quantities in response to the data storagequantities, whereby the increase of the quantities in which data arestored in the buffers can be suppressed. As a result, the increase ofthe delay time caused when inputted data are multiplexed can be avoided,and the disadvantage such as a failure of synchronization on thereceiving side can be prevented.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram showing an arrangement of a digital satellitebroadcasting system according to a first embodiment.

FIG. 2 is a block diagram showing an arrangement of a multiplexingapparatus.

FIG. 3 is a block diagram showing an arrangement of a rate-variable typemultiplexing buffer.

FIG. 4 is a block diagram showing other arrangement of the rate-variabletype multiplexing buffer.

FIG. 5 is a block diagram showing an example of an arrangement of a rateconverting section provided within the rate-variable type multiplexingbuffer.

FIG. 6 is a diagram showing an arrangement of a 1-bit converting sectionprovided within the rate converting section.

FIG. 7 is a diagram to which reference will be made in explaining arelationship among respective signals in the 1-bit switching section.

FIG. 8 is a diagram showing an arrangement of an n-bit switching sectionprovided within the rate converting section.

FIG. 9 is a diagram to which reference will be made in explaining arelationship among respective signals in the n-bit switching section.

FIG. 10 is a diagram to which reference will be made in explaining themanner in which the rate converting section is operated.

FIG. 11 is a diagram to which reference will be made in explaining themanner in which the rate converting section and the barrel shifter areoperated.

FIG. 12 is a block diagram showing an arrangement of a multiplexingapparatus according to a second embodiment.

FIG. 13 is a diagram to which reference will be made in explaining themanner in which rates are varied by using priority information.

FIG. 14 is a block diagram showing an arrangement of a multiplexingapparatus according to a third embodiment.

FIGS. 15A to 15C are diagrams to which reference will be made inexplaining arrangements of TS packets of MPEG2 and PES packets.

FIG. 16 is a diagram to which reference will be made in explaining themanner in which the inputted signal rate is fluctuated when inputteddata are multiplexed.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 shows an arrangement of a digital satellite broadcasting system100 according to a first embodiment.

This broadcasting system 100 may include video encoders 111A to 111C forcompression-coding video signals Va to Vc according to the MPEGstandard, respectively, a multiplexing apparatus 114 for outputting atransport stream TS by assembling video data (PES packets of video data)PESa to PESc outputted from the video encoders 111A to 111C andmultiplexing these packets, a transmitting apparatus 115 for digitallymodulating this transport stream TS and up-converting the modulatedtransport stream to a predetermined frequency band to provide abroadcasting signal and a transmitting antenna 116 for transmitting thisbroadcasting signal to a satellite 120.

Incidentally, the video data PESa to PESc are parallel data of byteunit, respectively. Although not shown in FIG. 15B, in actual practice,an 16 byte error-correcting party may be added to each TS packet (188bytes), and the error-correcting parity may be used to correct errors onthe receiving side. Video data PESa to PESc that are reproduced by areproducing apparatus such as a disc apparatus may be supplied to themultiplexing apparatus 114 instead of the video data PESa to PEScgenerated by the video encoders 111A to 111C.

Also, the broadcasting system 100 may include a receiving antenna 117for receiving a broadcasting signal transmitted from the satellite 120,a receiving apparatus 118 for generating a video signal Vo of apredetermined program by demodulating and decoding the broadcastingsignal received at this receiving antenna 117 and a monitor 119 fordisplaying an image based on this video signal Vo.

In the above-mentioned arrangement, the video encoders 111A to 111C onthe transmitting side may generate the video data PESa to PESc bycompression-coding the video signals Va to Vc, respectively. The videodata PESa to PESc may be supplied to the multiplexing apparatus 114. Themultiplexing apparatus 114 may assemble the video data PESa to PESc toprovide TS packets and then may multiplex these packets to provide anMPEG2 transport stream TS. This transport stream TS may be supplied tothe transmitting apparatus 115.

The transmitting apparatus 115 may generate a broadcasting signal bydigitally modulating and up-converting the transport stream TS. Then,this broadcasting signal may be supplied to the transmitting antenna116, and this broadcasting signal may be transmitted from thetransmitting antenna 116 to the satellite 120.

Also, the broadcasting signal transmitted from the satellite 120 may bereceived at the receiving antenna 117 on the receiving side, and thebroadcasting signal thus received may be supplied to the receivingapparatus 118. This receiving apparatus 118 may generate the videosignal Vo of the predetermined program by demodulating and decoding thereceived broadcasting signal. Then, this video signal Vo may be suppliedto the monitor 119, and the monitor 119 may display the image based onthe video signal Vo.

FIG. 2 shows an arrangement of the multiplexing apparatus 114. Thismultiplexing apparatus 114 may include input terminals 130A to 130C towhich the video data PESa to PESc may be inputted from the videoencoders 111A to 111C and rate-variable type multiplexing buffers 132Ato 132C for sequentially outputting data PDa to PDc comprising the TSpackets by writing the video data PESa to PESc in the buffers andreading out the same from the buffers.

Also, the multiplexing apparatus 114 may include a multiplexing circuit133 which may generate the TS packets by adding the error-correctingparity to the packet headers to the data PDa to PDc after the packetheaders were added to the data and which may generate the transportstream TS by multiplexing the TS packets, an output terminal 134 fromwhich the transport stream TS may be outputted, a multiplexing controlsection 135 for controlling operations of the rate-variable typemultiplexing buffers 132A to 132C and the multiplexing circuit 133 andan input terminal 136 to which transmission rate information TRIsupplied from the transmitting apparatus 115 may be inputted. Thetransmission rate information TRI inputted to the input terminal 136 maybe supplied to the multiplexing control section 135.

FIG. 3 shows an arrangement of the rate-variable type multiplexingbuffer 132A. This rate-variable type multiplexing buffer 132A mayinclude an input terminal 141 to which the video data PESa may beinputted, a parallel-to-serial converter (hereinafter referred to as“P/S converter”) 142 for converting the video data PESa inputted to thisinput terminal 141 in the form of parallel data of byte unit to serialdata and a serial data buffer 143 for writing and storing the serialdata outputted from this P/S converter 142. The buffer 143 may have adata storage quantity detecting function, and detected storage quantityinformation DSI may be supplied to the multiplexing control section 135.

Also, the rate-variable type multiplexing buffer 132A may include aserial-to-parallel converter (hereinafter referred to as “S/Pconverter”) 144 for converting serial data read out from the serial databuffer 143 into parallel data of byte unit to provide data PDa asoutputted data and an output terminal 145 from which the data PDaobtained at this S/P converter 144 may be outputted.

Also, the rate-variable type multiplexing buffer 132A may include a dataanalyzing section 146 for analyzing the video data PESa inputted to theinput terminal 141 and a rate-variable control section 147 which maysuppress the data storage quantity of the buffer 143 from beingincreased by controlling the buffer 143 in response to the increase ofthe data storage quantity of the buffer 143 under control of themultiplexing control section 135 such that data may be selectively readout from the buffer 143.

Although not described above, the video data PESa might be the PESpacket of video data, and image data provided in the payload might besuch one that data is processed by a discrete cosine transformation(DCT: discrete cosine transformation) at the block unit of 8 pixels×8lines, a resultant DCT coefficient is quantized, and the DCT coefficientis variable-length-coded by scanning such as zigzag scanning. The dataanalyzing section 146 may analyze which portion of the video data PESa,for example, relates to which order of the DCT coefficient. Then, ananalyzed result may be supplied from this data analyzing section 146 tothe rate-variable control section 147. The rate-variable control section147 may control the buffer 143 with reference to the analyzed resultsuch that DCT coefficients of high-order may be discarded when storeddata may be read out from the buffer. In this case, as the data storagequantity increases, the minimum order of the discarded DCT coefficientis lowered, thereby resulting in the data storage quantity beingsuppressed from being increased.

Also, the rate-variable type multiplexing buffer 132A may include astart sync code detecting section 148 for detecting a start sync codefrom data stored in the serial data buffer 143 and a byte alignmentsection 149 for controlling the S/P converter 144 based on the detectedoutput SCD from the start sync code detecting section 148 such that thedata PDa outputted from the S/P converter 144 may complete the byte datain front of the start sync code.

As is well-known, MPEG2 video encoded data may have a hierarchyarrangement ranging from the sequence layer to the block layer. Then,the sync start code is provided at the leading portion of the layer overthe slice layer. Each sync code may be formed of 4 bytes, and 3 bytesfrom the leading portion may be “00 00 01 (H)”. Accordingly, the startsync code detecting section 148 may detect the start sync code bydetecting the 3-byte portion by a method such as pattern matching.

An operation of the rate-variable type multiplexing buffer 132A shown inFIG. 3 will be described next. The video data PESa inputted to the inputterminal 141 may be converted by the P/S converter 142 in the form ofparallel data of byte unit to serial data and then supplied to thebuffer 143, in which it is written and stored.

Also, the video data PESa inputted to the input terminal 141 may besupplied to the data analyzing section 146 and thereby data may beanalyzed. The data analyzing section 146 may analyze which portion ofthe video data PESa relates to which order of DCT coefficient. Theanalyzed result may be supplied to the rate-variable control section147.

The data stored in the buffer 143 may be read out from the buffer undercontrol of the multiplexing control section 135. In this case, althoughthe reading of data stored in the buffer 143 may be limited inconsideration of a balance between the reading of data stored in otherrate-variable type multiplexing buffers 132B, 132C and a transmissionrate indicated by the transmission rate information TRI, when the datastorage quantity of the buffer 143 increases, stored data may beselectively read out under control of the rate-variable control section147 with reference to the analyzed result of the data analyzing section146, thereby resulting in the data quantity being reduced. For example,the data quantity can be reduced by discarding the DCT coefficients ofhigh-orders. In this case, the minimum order of DCT coefficient may belowered as the data storage quantity increases. Thus, the increase ofthe data storage quantity of the buffer 143 can be suppressed, and theincrease of the delay time caused when inputted data are multiplexed canbe avoided.

The S/P converter 144 may convert the data read out from the buffer 143in the form of serial data to parallel data of byte unit to provide thedata PDa. This data PDa may be led out to the output terminal 145. Inthis case, the start sync code of the MPEG2 encoded code may be detectedfrom the data stored in the buffer 143. The byte alignment section 149may control the operation of the S/P converter 144 based on the detectedoutput SCD. Consequently, the data PDa outputted from the S/P converter144 may be such that byte data may be completed in front of each startsync code.

Referring back to FIG. 2, although not described in detail, therate-variable type multiplexing buffers 132B, 132C also may be arrangedsimilarly to the above-mentioned rate-variable type multiplexing buffer132A and operated similarly, thereby resulting in the data PDb, PDcbeing outputted sequentially.

An operation of the multiplexing apparatus 114 shown in FIG. 2 will bedescribed. The video data PESa may be supplied from the input terminal130A to the rate-variable type multiplexing buffer 132A, and data PDacomprising the TS packets may be sequentially outputted from thisrate-variable type multiplexing buffer 132 a. Also, the video data PESbmay be supplied from the input terminal 130B to the rate-variable typemultiplexing buffer 132B, and data PDb comprising the TS packets may besequentially outputted from this rate-variable type multiplexing buffer132 b. Further, the video data PESc may be supplied from the inputterminal 130C to the rate-variable type multiplexing buffer 132C, andthe data PDc comprising the TS packets may be sequentially outputtedfrom this rate-variable type multiplexing buffer 132C.

The data PDa to PDc outputted from the rate-variable type multiplexingbuffers 132A to 132C may be supplied to the multiplexing circuit 133.This multiplexing circuit 133 may generate TS packets by adding thepacket header and the error-correcting parity to the data PDa to PDc.Also, the multiplexing circuit 133 may generate the transport stream TSby multiplexing TS packets generated from the data PDa to PDc. Thistransport stream TS may be led out to the output terminal 134.

As described above, according to the first embodiment, in therate-variable type multiplexing buffers 132A to 132C (see FIG. 3) of themultiplexing apparatus 114, the stored data may be selectively read outfrom the serial data buffer 143 in response to the data storagequantity. For example, when the data storage quantity increase, the dataquantity may be reduced by discarding the DCT coefficients ofhigh-order. Thus, even when the video data PESa to PESc are of thevariable-rate video data, the increase of the data storage quantity ofthe buffer 143 can be suppressed, and the increase of the delay timecaused when inputted data are multiplexed can be avoided, thereby makingit possible to prevent a disadvantage such as a failure ofsynchronization on the receiving side.

Incidentally, the rate-variable type multiplexing buffers 132A to 132Cneed not always be arranged as shown in FIG. 3 but can be arranged asshown in FIG. 4. A rate-variable type multiplexing buffer 132A′ shown inFIG. 4 will be described.

This rate-variable type multiplexing buffer 132A′ may include an inputterminal 151 to which the video data PESa may be inputted, atime-adjustment delay section 152 for delaying the video data PESainputted to this input terminal 151 by a predetermined time and aparallel data buffer 153 in which the video data PESa delayed by thedelay section 152 may be written and stored. The buffer 153 may have adata storage quantity detecting function, and storage quantityinformation DSI may be supplied to the multiplexing control section 135.

Also, the rate-variable type multiplexing buffer 132A′ may include adata analyzing section 154 for generating bit enable data D1 to Dnindicative of validity or invalidity of bit data of each byte of thevideo data PESa stored in the above-mentioned buffer 153 in response toa plurality of (n) data reduction ratios by analyzing the video dataPESa supplied to the input terminal 151 and which may detect the startsync code from the video data PESa by a method such as pattern-matchingand a plurality of bit enable buffers 155-1 to 155-n in which data D1 toDn may be written at the byte unit and stored.

In the data D1 to Dn, “1”, for example, assumes validity and “0” assumesinvalidity. Also, the data analyzing section 154 may analyze whichportion of the video data PESa, for example, relates to which order ofthe DCT coefficient, and may generate the data D1 to Dn in response to aplurality of data reduction ratios such that the DCT coefficientportions higher than a predetermined order in the video data PESa may bemade invalid. In this case, as the data reduction ratio becomes high,the minimum order of the DCT coefficient which will be made invalid islowered.

Also, the rate-variable type multiplexing buffer 132A′ may include anenable control section 156 for selectively outputting any one of thedata D1 to Dn read out from the buffers 155-1 to 155-n in response tothe data storage quantity under control of the multiplexing controlsection 135 and a rate converting section 157 for discarding invalid bitdata from the bit data of each byte of the video data PESa read out fromthe buffer 153 by using the bit enable data D outputted from the enablecontrol section 156.

Incidentally, data may be read out from the buffer 153 under control ofthe multiplexing control section 135. Data may be written in and readout from the buffers 155-1 to 155-n in response to the manner in whichdata may be written and read out from the buffer 153. The delay time ofthe delay section 152 may be set in such a manner that the bit enabledata D corresponding to the bit data of each byte of the video data PESasupplied to the buffer 153 may be supplied to the rate convertingsection 157.

Also, the rate-variable type multiplexing buffer 132A′ may include abarrel shifter 158 for generating the data PDa as outputted data byconverting data outputted from the rate converting section 157, i.e.valid bit data of each byte of the video data PESa into parallel data ofbyte unit, an output terminal 159 from which the data PDa may beoutputted and a byte alignment section 160 for controlling the operationof the barrel shifter 158 on the basis of the detected output SCD of thestart sync code from the data analyzing section 154 such that the dataPDa outputted from the barrel shifter 158 may complete the byte data infront of the start sync code.

As described above, the rate converting section 157 may discard invalidbit data from bit data of each byte of the video data PESa. To beconcrete, the rate converting section 157 may generate byte data inwhich valid bit data are aligned to the MSB (most significant bit) sidein response to each byte data of the video data PESa and other bit dataare set to “0” and valid bit data length information N. The barrelshifter 158 may generate parallel data of byte unit by using the bytedata BYD and the data length information N supplied from the rateconverting section 157.

FIG. 5 shows an example of an arrangement of the rate converting section157. This rate converting section 157 may comprise a 1-bit switchingsection 171 to an 8-bit switching section 178 and a ROM table 179. Bitdata of each byte of the video data PESa assume a7 to a0, and bit dataof each bit enable data D of the byte unit assume b7 to b0.

The bit data a0 may be supplied to the 1-bit switching section 171 asthe inputted signal and the bit data b0 may be supplied thereto as thecontrol signal. Output signals from the 1-bit switching section 171 tothe 7-bit switching section 177 and the bit data a1 to a7 may besupplied to the 2-bit switching section 172 to the 8-bit switchingsection 178 as the inputted signals and the bit data b1 to b7 may besupplied thereto as the control signals. Then, the 8-bit switchingsection 178 may output the byte data BYD (c7 to c0). The bit data b7 tob0 may be supplied to the ROM table 179 as the inputted signals and theROM table 179 may generate the data length information N indicating thenumber of “1” of the bit data b7 to b0.

FIG. 6 shows an arrangement of the 1-bit switching section 171. This1-bit switching section 171 may be a change-over switch including twofixed terminals f0, f1 and a movable terminal g1. “0” may be supplied tothe fixed terminal f0 and the inputted signal a0 may be supplied to thefixed terminal f1 so that the outputted signal may be outputted from themovable terminal g1. When the control signal b0 is held at “1”, themovable terminal g1 may be connected to the fixed terminal f1 to therebyoutput the inputted signal a0 as the outputted signal. When on the otherhand the control signal b0 is held at “0”, the movable terminal g1 maybe connected to the fixed terminal f0 to thereby output “0” as theoutputted signal. FIG. 7 shows a relationship among the respectivesignals in the 1-bit switching section 171.

FIG. 8 shows an arrangement of an n (n=2 to 8) bit switching section170. This n-bit switching section 170 may be a change-over switch having(n+1) fixed terminals f0, f1, f2, . . . , fn−1, fn and n movableterminals g1, g2, . . . , gn−1, gn. “0” may be supplied to the fixedterminal f0, the inputted signals I1, I2, . . . , In−1, In may besupplied to the fixed terminals f1, f2, . . . , fn−1, fn, and outputtedsignals O1, O2, . . . , On−1, On may be outputted from the movableterminals g1, g2, . . . , gn−1, gn.

When the above-mentioned switching section may be the 2-bit switchingsection 172, it may be a change-over switch having three fixed terminalsf0, f1, f2 and two movable terminals g1, g2. Then, “0” may be suppliedto the fixed terminal f0, the outputted signal of the 1-bit switchingsection 171 may be supplied to the fixed terminal f1 as the inputtedsignal I1, the signal a1 may be supplied thereto as the inputted signal12, and the outputted signals O1, O2 may be outputted from the movableterminals g1, g2.

Also, when the above-mentioned switching section may be the 8-bitswitching section 178, for example, it may be the change-over switchhaving 9 fixed terminals f0, f1, f2, . . . , f8 and 8 movable terminalsg1, g2, . . . , g8. Then, “0” may be supplied to the fixed terminal f0,the outputted signals O1, O2, . . . , O7 of the 7-bit switching section171 may be supplied to the fixed terminals f1, f2, . . . , f7 as theinputted signals I1, I2, . . . , I7, the signal a7 may be suppliedthereto as the inputted signal 18 and outputted signals O1, O2, . . . ,O8 comprising byte data BYD [c0 to c7] may be outputted from the movableterminals g1, g2, . . . , g8.

When the control signal is held at “1”, the movable terminals g1, g2, .. . , gn−1, gn may be respectively connected to the fixed terminals f1,f2, . . . , fn−1, fn, whereby the inputted signals I1, I2, . . . , In−1,In may be outputted as the outputted signals O1, O2, . . . , On−1, On asthey are. When on the other hand the control signal is held at “0”, themovable terminals g1, g2 . . . , gn−1, gn may be respectively connectedto the fixed terminals f0, f1, . . . , fn−2, fn−1, whereby the signal“0” may be outputted as the outputted signal O1 and the inputted signalsI1, . . . , In−2, In−1 may be outputted as the outputted signals O2, . .. , On−1, On, respectively. FIG. 9 shows a relationship among respectivesignals in the n-bit switching section 170 where I0=“0”.

FIG. 10 shows an example of the manner in which the rate convertingsection 157 may generate byte data BYD. This example assumes that bitdata [a7 to a0] of the video data PESa are [10110111] and that bit data[b7 to b0] of the bit enable data D are [00101110]. In this example,[1011000] may be generated as the byte data BYD [c7 to c0]. This datamight be such data in which valid bit data of the bit data [a7 to a0]are aligned to the MSB side and other bit data are set to “0”. In thecase of this example, the data length information N outputted from theROM table 179 may indicate 4.

FIG. 11 shows examples of data stored in the bit enable buffer and theparallel data buffer 153 selected by the enable control section 156,data outputted from the rate converting section 157 and data outputtedfrom the barrel shifter 158.

An operation of the rate-variable type multiplexing buffer 132A′ shownin FIG. 4 will be described next. The video data PESa inputted to theinput terminal 151 may be supplied through the delay section 152 to theparallel data buffer 153, in which it may be written at the byte unitand stored. Also, the video data PESa inputted to the input terminal 151may be supplied to and analyzed by the data analyzing section 154. Then,this data analyzing section 154 may generate the bit enable data D1 toDn indicative of validity or invalidity of bit data of each byte of thevideo data PESa stored in the above-mentioned buffer 153 in response toa plurality of (n) data reduction ratios.

The data analyzing section 154 may analyze which portion of the videodata PESa, for example, may concern which order of the DCT coefficient,and may generate the data D1 to Dn in response to a plurality of datareduction ratios such that the portions of DCT coefficients higher thanthe predetermined order in the video data PESa may be made invalid. Thebit enable data D1 to Dn may be supplied to the bit enable buffers 155-1to 155-n, in which they are written at the byte unit and stored.

The data stored in the buffer 153 and the bit enable data of the buffers155-1 to 155-n may be read out in synchronism with each other undercontrol of the multiplexing control section 135. Then, any one of thedata D1 to Dn read out respectively from the buffers 155-1 to 155-n maybe selected by the enable control section 156 and then fed to the rateconverting section 157.

The rate converting section 157 may discard invalid bit data from thebit data of each byte of the video data PESa read out from the buffer153 by using the bit enable data D outputted from the enable controlsection 156. That is, the rate converting section 157 may generate thebyte data BYD in which valid bit data are aligned to the MSB side inresponse to each byte data of the video data PESa and the valid bit datalength information N.

The byte data BYD and the valid bit data length information N generatedfrom the rate converting section 157 may be supplied to the barrelshifter 158. This barrel shifter 158 may convert the valid bit data ofeach byte of the video data PESa into parallel data of byte unit basedon the byte data BYD and the data length information N to output thedata PDa as outputted data. Then, this data PDa may be led out to theoutput terminal 159.

The data analyzing section 154 may detect the start sync code of theMPEG2 encoded data from the video data PESa, and the byte alignmentsection 160 may control the operation of the barrel shifter 158 on thebasis of the detected output SCD. Thus, the data PDa outputted from thebarrel shifter 158 may complete the byte data in front of each startsync code.

Although not described above, while the reading of data stored in thebuffer 153 may be limited in consideration of a balance between thereading of data stored in other rate-variable type multiplexing buffersand the transmission rate indicated by the transmission rate informationTRI, when the data storage quantity of the buffer 153 increases, undercontrol of the multiplexing control section 153, the enable controlsection 156 may select bit enable data with a high data reduction ratio,thereby resulting in the data quantity being reduced. In this case, thebit enable data with higher data reduction ratio may be selected as theincrease of the data storage quantity becomes large. Thus, the increaseof the data storage quantity of the buffer 153 can be suppressed, andthe increase of the delay time caused when inputted data are multiplexedcan be avoided.

As described above, in the rate-variable type multiplexing buffer 132A′shown in FIG. 4, the enable control section 156 may select the bitenable data with the predetermined data reduction ratio in response tothe storage quantity of the parallel data buffer 153, and the rateconverting section 157 may selectively discard bit data. For example,when the data storage quantity increases, the data quantity can bereduced by discarding DCT coefficients of high-order. Accordingly, evenwhen the video data PESa is of the variable rate video data, theincrease of the data storage quantity of the buffer 153 can besuppressed and the increase of the delay time caused when inputted dataare multiplexed can be avoided. Thus, it is possible to prevent adisadvantage such as a failure of synchronization on the receiving side.Also, as compared with the rate-variable type multiplexing buffer 132Ashown in FIG. 3, the P/S converter and the S/P converter can beeliminated and hence the scale of hardware can be reduced.

A second embodiment according to this invention will be described next.FIG. 12 shows an arrangement of a multiplexing apparatus 114A accordingto the second embodiment. In FIG. 12, elements and parts correspondingto those of FIG. 2 are marked with the same reference numerals, andtherefore need not be described in detail.

This multiplexing apparatus 114A may include input terminals 136A to136C to which priority information PRa to PRc outputted from the videoencoders 111A to 111C may be inputted, respectively. Then, the priorityinformation PRa to PRc inputted to the input terminals 136A to 136C maybe supplied to the multiplexing control section 135.

The multiplexing control section 135 may control not only the increaseof the data storage quantities of the data buffers within the respectiverate-variable type multiplexing buffers 132A to 132C but also the datareduction quantities in the respective rate-variable type multiplexingbuffers 132A to 132C based on the priority information PRa to PRc sothat an output rate of the transport stream TS outputted from themultiplexing circuit 133 (hereinafter simply referred to as “outputrate”) may be matched to a transmission rate indicated by thetransmission rate information TRI.

A rest of the multiplexing apparatus 114A shown in FIG. 12 is arrangedsimilarly to the multiplexing apparatus 114 shown in FIG. 2, and isoperated similarly. While the priority information may be inputted tothe multiplexing apparatus 114A independently of the video data PESa toPESc as described above, the present invention is not limited theretoand video data PESa to PESc which contain the priority information PRato PRc may be inputted to the multiplexing apparatus. In that case, themultiplexing apparatus needs a separating section for separating thepriority information PRa to PRc from the video data PESa to PESc.

FIG. 13 shows an example of the manner in which the multiplexingapparatus 114A shown in FIG. 12 is operated. In this example, the ratesof the video data PESa to PESc are assumed to be the same fixed ratesand R1 assume the total sum of rates. Also, it is assumed that theinitial transmission rate and other data and redundant data are notmultiplexed with each other. Then, the priority of the video data PESato PESc is assumed to be PESa>PESb>PESc, and the video data PESa has thehighest priority.

When the transmission rate is varied from R1 to R2 on the multiplexingapparatus 114A at a time t1, the multiplexing apparatus 114A may varythe transmission rate by reducing the data quantities of the video dataPESa to PESc in response to the priority information PRa to PRc. Then,under control, the output rate may be matched with the transmission rateR2 at a time t2 by matching the output rate with the transmission rateR2. In this example, the data quantity of the video data PESc with thelowest priority may be reduced most. Thus, it is possible to prevent thequality of the video data PESa with the high priority from beingdeteriorated.

Assuming that Δt(=t2−t1) represents a time required to vary the rate,then when there is used a method of feeding the rate change back to eachencoder, the video encoder cannot cope with the rate change until thetransmission of data stored in the buffer on the encoder side iscompleted. Even the MPEG2 variable-rate encoder requires a time longerthan a slice layer unit (about 1.1 ms in the NTSC system) in order tovary the rate. The delay of such control may cause extra data to begenerated depending upon a difference between inputted and outputtedrates in the multiplexing apparatus.

Although extra data may be stored in the buffer and it seems that suchextra data may be absorbed, such extra data may appear in the form ofthe increase of the delay amount of the data itself. This increase ofthe delay amount may become a factor which causes a synchronization tobe failed on the receiving side. During the time period Δt, since themultiplexing apparatus 114A shown in FIG. 12 may change the rate byreducing the data quantities within the respective rate-variable typemultiplexing buffers 132A to 132C real time, the delay time of the dataitself becomes a very small time period of approximately a processingclock unit (less than 1 μs). Therefore, there may not arise a problem atall due to the delay of data within the respective variable-rate typemultiplexing buffers 132A to 132C.

A third embodiment according to this invention will be described next.FIG. 14 shows an arrangement of a multiplexing apparatus 114B accordingto the third embodiment. In FIG. 14, elements and parts corresponding tothose of FIG. 12 are marked with the same reference numerals andtherefore need not be described in detail. This multiplexing apparatus114B is able to convert the rate as its own function and may furtherinclude means for feeding the rate change back to each encoder.

This multiplexing apparatus 114B may include output terminals 137A to137C from which rate control signals RCSa to RCSc outputted from themultiplexing control section 135 may be outputted. Then, the ratecontrol signals RCSa to RCSc outputted to the output terminals 137A to137C may be supplied respectively to the video encoders 111A to 111C.

In this case, until the video encoders 111A to 111C complete the ratechange, in order to prevent the delay amount of data from beingincreased, the multiplexing apparatus 114B may change the rate byreducing the data quantities within the respective rate-variable typemultiplexing buffers 132A to 132C. Of course, if the rate change iscompleted in the video encoders 111A to 111C, then at the time point inwhich the rate change is finished, the total sum of inputted rates ofthe video data PESa to PESc supplied to the multiplexing apparatus 114Bmay be matched with the transmission rate with the result that the rateis not varied in the multiplexing apparatus 114B.

According to this invention, a plurality of outputted data may beobtained by effecting a data quantity reduction processing on datastored in a plurality of buffers in response to each data storagequantity, and multiplexed data may be obtained by multiplexing aplurality of outputted data. Therefore, the increase of the delay timecaused when inputted data are multiplexed can be avoided, and thedisadvantage such as the failure of synchronization on the receivingside can be prevented.

INDUSTRIAL APPLICABILITY

As described above, since the data multiplexing apparatus according tothis invention can obtain a plurality of outputted data by effecting thedata quantity reduction processing on the data stored in a plurality ofbuffers in response to the respective data quantities and can obtainmultiplexed data by multiplexing a plurality of outputted data, thepresent invention may be suitably applied to a digital satellitebroadcasting system in which video and audio signals are digitallycompression-coded according to the MPEG standard or the like and the bitstream obtained by the multiplexing according to the MPEG standard orthe like can be transmitted through the satellite.

1. A data multiplexing apparatus comprising: a plurality of buffers forrespectively storing a plurality of inputted data, each of saidplurality of buffers including a start sync code detecting section, aserial data buffer and a byte alignment section; a storage quantitydetecting means for detecting data storage quantities of said pluralityof buffers; output data generating means for generating a plurality ofoutputted data by effecting a data quantity reduction processing on datastored in said plurality of buffers; and data multiplexing means forobtaining multiplexed data by multiplexing said plurality of outputteddata.
 2. A data multiplexing apparatus as claimed in claim 1, whereinsaid output data generating means generates said plurality of outputteddata by effecting a data quantity reduction processing on the datastored in said plurality of buffers in response to the data storagequantities of said plurality of buffers and the transmission rateconcerning said multiplexed data.
 3. A data multiplexing apparatus asclaimed in claim 1, wherein said output data generating means generatessaid plurality of outputted data by effecting a data quantity reductionprocessing on the data stored in said plurality of buffers in responseto the data storage quantities of said plurality of buffers andpriorities of said plurality of inputted data.
 4. A data multiplexingapparatus as claimed in claim 1, wherein said plurality of inputted dataare data compressed by using a discrete cosine transformation and saidoutput data generating means reduces said data quantity by discardinghigh-order coefficients of said discrete cosine transformation.
 5. Adata multiplexing apparatus as claimed in claim 1, wherein said outputdata inputted data are parallel data of byte unit and said buffers areserial buffers and said data multiplexing apparatus further comprisesparallel-to-serial converting means for converting said inputted data inthe form of parallel data of byte unit to serial data andserial-to-parallel converting means for converting data read out fromsaid buffer in the form of serial data to parallel data of byte unit andwherein said output data generating means reduces said data quantity byselectively reading out data stored in said serial data buffer.
 6. Adata multiplexing apparatus as claimed in claim 5, wherein said inputteddata are MPEG2 encoded data and said start sync code detecting sectiondetects a start sync code from said encoded data and said byte alignmentsection controls said serial-to-parallel converting means based on adetected output from said start sync code detecting section such thatsaid outputted data complete byte data in front of said start sync code.7. A data multiplexing apparatus as claimed in claim 1, wherein saidinputted data is parallel data of one byte width and said buffer is aparallel data buffer and said data multiplexing apparatus furthercomprises a data analyzing section for analyzing said inputted data andgenerating data indicative of validity or invalidity of bit data of eachbyte stored in said parallel data buffer in response to a plurality ofdata reduction ratios and a plurality of bit enable buffers forrespectively storing said data indicative of validity or invaliditygenerated in response to said plurality of data reduction ratios andwherein said output data generating means selects any one of saidplurality of bit enable buffers in response to said buffer data storagequantity and outputs said outputted data by only producing valid bitdata from the bit data of each byte of data read out from said buffer onthe basis of data from said selected bit enable buffer.
 8. A datamultiplexing apparatus as claimed in claim 7, wherein said inputted dataare MPEG2 encoded data and said data multiplexing apparatus furthercomprises start code detecting means for detecting a start code fromsaid encoded data and byte alignment means for controlling saidoutputted data on the basis of the detected output from said start codedetecting means such that byte data are completed in front of said startcode.
 9. A data multiplexing method comprising the steps of: storing aplurality of inputted data in a plurality of buffers, each of saidplurality of buffers including a start sync code detecting section, aserial data buffer and a byte alignment section; detecting storagequantities of said plurality of buffers; obtaining a plurality ofoutputted data by effecting a data quantity reduction processing on thedata stored in said plurality of buffers in response to the data storagequantities of said plurality of buffers; and generating multiplexed databy multiplexing said plurality of outputted data.
 10. A datamultiplexing apparatus as claimed in claim 9, wherein said process forgenerating said plurality of outputted data generates a plurality ofoutputted data by effecting a data quantity reduction processing on thedata stored in said plurality of buffers in response to the data storagequantities of said plurality of buffers and a transmission rateconcerning said multiplexed data.
 11. A data multiplexing apparatus asclaimed in claim 9, wherein said process for generating said pluralityof outputted data generates a plurality of outputted data by effecting adata quantity reduction processing on the data stored in said pluralityof buffers in response to the data storage quantities of said pluralityof buffers and priorities of said plurality of inputted data.
 12. A datamultiplexing apparatus as claimed in claim 9, wherein said plurality ofinputted data are data compressed by using a discrete cosinetransformation and said process for generating said plurality ofoutputted data reduces said data quantity by discarding high-ordercoefficients of said discrete cosine transformation.
 13. A datamultiplexing apparatus as claimed in claim 9, wherein said inputted dataare parallel data of byte unit and said buffer is a serial data bufferand said data multiplexing method further comprises the steps convertingsaid inputted data in the form of parallel data of byte unit to serialdata and inputting said serial data into said buffer and converting thedata read out from said buffer in the form of serial data to paralleldata of byte unit and generating said parallel data as said outputteddata and wherein said process for generating said plurality of outputteddata reduces said data quantity by selectively reading out stored datafrom said serial data buffer in response to the data storage quantity ofsaid buffer.
 14. A data multiplexing apparatus as claimed in claim 13,wherein said inputted data are MPEG2 encoded data and said plurality ofbuffers detect said start sync code from said encoded data and controlsaid outputted data on the basis of said detected start sync code suchthat byte data is completed in front of said start sync code.
 15. A datamultiplexing apparatus as claimed in claim 9, wherein said inputted dataare parallel data of one byte width and said buffer is a parallel databuffer and said data multiplexing method further comprises the steps ofgenerating data indicative of validity or invalidity of bit data of eachbyte stored in said parallel data buffer and storing said dataindicative of said validity or invalidity generated in response to saidplurality of data reduction ratios in a plurality of bit enable buffersand wherein said process for obtaining said plurality of outputted dataselects any one of said plurality of bit enable buffers in response tosaid buffer data storage quantity and generating said outputted data byreading only valid bit data from the bit data of each byte of the dataread out from said buffer on the basis of data from said selected bitenable buffer.
 16. A data multiplexing apparatus as claimed in claim 15,wherein said inputted data are MPEG2 encoded data and said datamultiplexing method further comprises the steps of detecting a startcode from said encoded data and controlling said outputted data on thebasis of said detected start code such that byte data are completed infront of said start code.
 17. A data transmitting apparatus including adata multiplexing section for generating multiplexed data bymultiplexing a plurality of inputted data and a data transmittingsection for transmitting said multiplexed data, said data multiplexingsection comprising: a plurality of buffers for storing a plurality ofinputted data, each of said plurality of buffers including a start synccode detecting section, a serial data buffer and a byte alignmentsection; a storage quantity detecting means for detecting data storagequantities of said plurality of buffers; output data generating meansfor generating a plurality of outputted data by effecting a dataquantity reduction processing on data stored in said plurality ofbuffers in response to data storage quantities of said plurality ofbuffers; and data multiplexing means for obtaining multiplexed data bymultiplexing said plurality of outputted data.
 18. A data transmittingapparatus according to claim 17, further comprising a plurality ofencoders for generating a plurality of inputted data.